Conventionally, to facilitate lower processor power consumption, techniques of controlling the frequency of clock signals supplied to the processor are commonly known (for example, refer to Japanese Laid-Open Patent Publication No. 2007-317054). Further, to facilitate lower processor power consumption, techniques of controlling the value of supply voltage and the frequency of clock signals supplied to the processor are commonly known (for example, refer to Japanese Laid-Open Patent Publication No. 2009-175788).
A technique of facilitating lower power consumption of a virtual server system is commonly known where a management apparatus of the virtual server system uses server hardware information and virtual server information built on a server to search for a virtual server suitable as a resource for the central processing unit (CPU) core count and memory capacity (for example, refer to Japanese Laid-Open Patent Publication No. 2010-61278).
Another technique is commonly known where power consumption values and processing performance values for a processor are estimated by simulation (for example, refer to David Brooks, et al, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations”, ISCA, 2000, p. 83-94).
Further, it is commonly known that when the operation states of processor elements change, power consumption lower than that by dynamic frequency scaling (DFS) performed to control frequency may be facilitated (for example, refer to Yasuko Eckert, et al, “Something Old and Something New: P-states can Borrow Microarchitecture Techniques Too”, ISLPED, 2012).
Nonetheless, in program execution, when conditions for processor power consumption values are set, a problem arises in that selection of an operation state by which the processor satisfies the conditions and by which processing performance is increased is difficult.